Computer Engineer · FPGA / Digital Design / Embedded Systems

Vincent Buff

My background spans digital design, computer architecture, and embedded systems, with a growing interest in AI/ML integration. I like working close to the silicon - the kind of problems where the hardware, the low-level code, and real-world signals all have to line up before anything works.

MS Computer Engineering, NC State '26 · Raleigh, NC
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Vincent Buff at his NC State graduation, in master's regalia on campus steps

About

I'm a computer engineer out of NC State's accelerated bachelor's-to-master's program. My coursework ran across embedded systems, computer architecture, and digital design. The common thread is hardware - the closer to the silicon, the more interesting the problem gets.

What pulls me in most is digital and FPGA design - writing RTL, verifying it, and getting a design running on real hardware. Most of that has come through graduate coursework and projects, with embedded and systems work layered in from two internships. I like the whole path, from an idea on paper to something actually running on a board.

Outside of pure engineering, I've always had a builder's streak. I've run a resale business, started a few small companies with friends, and I'm usually tinkering with some new project. I just like making things that work and solve a real problem.

Skills

A rough map of where I'm strongest, where I'm comfortable, and where I'm still learning.

Strongest / fluent

  • C / C++ - daily-driver languages
  • SystemVerilog - primary HDL for design + verification
  • RISC-V - deep ISA familiarity from grad coursework
  • Git · GitHub · VS Code - daily drivers

Comfortable

  • Python · Bash - scripting / glue
  • QuestaSim · Waveforms - simulation + verification
  • MCU / SBC platforms - MSP430, Jetson Xavier NX, Raspberry Pi
  • ARM architecture familiarity
  • Lab tooling: soldering, oscilloscopes, logic analyzers, 3D printing

Exposure

  • Xilinx Vivado / Vitis
  • Jenkins
  • Altium
  • CNC mills / PCB engravers (ECE Lab & Makerspace role)

Experience

Computer Engineer Intern

Northrop Grumman Mission Systems · Linthicum Heights, MD

May 2025 - July 2025

  • Built a centralized Common Config Repository for the Processing CTB team within CMAD, using Git submodules + sparse-checkout + custom bash to automate deployment workflows that previously required manual per-machine setup.
  • Contributed to the team's CI/CD pipeline across the VMWare Horizon + Atlassian stack.
  • Side prototype: Raspberry Pi 4B + ultrasonic sensors for real-time parking-overflow vehicle tracking, demoed end-to-end with on-device data capture.

Embedded Engineer Intern

Murano Corporation · Durham, NC

Dec 2023 - Aug 2024

  • Worked on a drone-detection embedded system targeting the Jetson Xavier NX, integrating a custom YOLO model in Python/Linux for real-time inference.
  • Cross-compiled Qt 5.15.0 for Raspberry Pi and Navy target devices, including the toolchain setup and dependency resolution.
  • 3D-modeled and printed prototype enclosures and mounts for team hardware.

Teaching Assistant + Lab Manager

NC State University · Raleigh, NC

2023 - 2025

  • Introduction to C Teaching Assistant - C programming fundamentals: pointers, memory management, and data structures.
  • ECE Lab & Makerspace Assistant Manager - supported student access to CNC mills, PCB engravers, 3D printers, and lab benches.

Projects

A mix of graduate coursework, my senior design capstone, and things I've built along the way. Each card links to a deeper write-up on how it was actually built.

Senior Design · Headline

Joystick-Controlled Radar Beamformer

CN0566 · ADAR1000 · HB100 · Raspberry Pi 4 · Python

Sponsored by Analog Devices. Designed a joystick-controlled interface for the CN0566 phased-array beamformer as a real-time demonstration tool for industry trade shows. Led hardware integration interfacing ADAR1000 beamforming ICs with the HB100 signal generator for precise per-element phase and gain control. Managed all Raspberry Pi 4 integration: environment setup, dependency management, library versioning, and device calibration. Debugged a silent cal-file fallback that surfaced at the anechoic chamber and got the system to first beam. Senior Design.

Read deep dive (PDF) →
Verification

I2CMB SystemVerilog Verification (Projects 2-4)

SystemVerilog · UVM-style · Functional Coverage

Built a layered testbench for an I2C master-bus controller across three project arcs: structural transactor → randomized test sequences → coverage closure. Three covergroups with fifteen coverpoints across Wishbone, I2C, and FSM. ECE 745.

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RTL Design

Synthesizable CNN Inference Pipeline

SystemVerilog · 12-state Read FSM · 5-state Write FSM

Hand-coded RTL for a CNN inference pipeline targeting fixed-window convolution. Designed dual-state-machine memory access, sized the line buffer to 2×1021 to handle the actual column count (a fix that surfaced from reading source carefully), and shipped 6/6 passing tests at 16ns clock period. ECE 564.

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Computer Architecture

Superscalar Out-of-Order Pipeline

C++ · 721sim · Rename + Issue + Retire

Implemented Projects 2-4 on Rotenberg's 721sim: register renaming, instruction issue, and squash/retire logic across eight cooperating structures. Covered the renamer, rename map table integration, branch checkpoints, and squash-on-mispredict recovery. ECE 721.

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FPGA Deployment

Early-Exit Inference Accelerator on ZCU102

PyTorch · Vitis AI · INT8 Quantization · VART · PetaLinux · Xilinx ZCU102

Deployed a PyTorch-trained ResNet-18 to the Xilinx ZCU102's DPU via the Vitis AI toolchain - end-to-end pipeline through INT8 quantization, model compilation, and PetaLinux deployment. Authored a multi-output C++ inference harness using VART runtime to extract per-exit confidence data across four early-exit branches, then collected a 5,000-inference CIFAR-10 dataset for offline analysis. Characterized per-exit DPU throughput by compiling four truncated sub-models, demonstrating up to 5.77× theoretical speedup over baseline ResNet-18 via confidence-based early termination. ECE 591.

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Simulation

Out-of-Order Processor Simulator

C++ · 9-stage Pipeline · 67 Architectural Registers

Solo C++ implementation of an out-of-order processor simulator: 9-stage pipeline, RMT/ROB, wakeup broadcast from Execute back to issue queue. 648 lines of sim_proc.cc with op-type-specific latencies (1/2/5 cycles). ECE 563.

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Embedded RTOS

Shields Up - Fault-Tolerant RTOS Build

RTXv5 · ARM Cortex-M · Custom HardFault Handler · Fault Injection

Hardened a multithreaded embedded system against a 15-fault catalog. Two ISRs, a custom HardFault handler, and seven RTXv5 threads across priority bands - including a watchdog thread at the lowest priority. ECE 560.

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Embedded

Autonomous Robotic Car

MSP430FR2355 · 5 ISRs · H-bridge PWM · IoT Telemetry

Junior-year embedded build on the MSP430FR2355: five ISRs feeding flags into a main loop, brushed DC motor control via H-bridge PWM, line-following FSM, and IoT telemetry. ECE 306.

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Other

Things I've built and led outside the classroom.

Pi Kappa Phi - Chapter President

NC State · Nov 2022 - Nov 2023

Led and managed the largest fraternity in North Carolina, overseeing a six-figure semesterly budget. Focused on building an open-dialogue environment and a healthier culture. Chapter earned Greek Village Community of the Year and Outstanding Leadership Development during my term.

Buff Brothers LLC

Founded 2025

Resale operation I founded in 2025. Started as a fraternity-brother Amazon-reimbursement model and transitioned to a fully solo operation by fall. A practical crash course in margins, logistics, and running a small business end to end.

Personal AI Executive Assistant

Ongoing

An AI assistant I'm building to help manage projects, writing, scheduling, and day-to-day organization. An ongoing experiment in AI tooling and automation.

Earlier ventures

All 2025, dissolved

Tip20 (tip-incentive consumer app), Smart Setup (small-biz websites + AI agents), Sweepsale (hyperlocal CV-assisted marketplace, with Dad). Each taught me something different about what's worth building.

Contact

Email vincent.m.buff@gmail.com LinkedIn linkedin.com/in/vincent-m-buff Resume Download PDF